UVM for FPGAs (Part 1): Get, Set, Go – Be Productive with UVM (USA timezone)

 UVM for FPGAs (Part 1): Get, Set, Go – Be Productive with UVM (US)

Srinivasan Venkataramanan, Entrepreneur and Head of VerifWorks

Thursday, September 9, 2021

11:00 AM – 12:00 PM PT

Register for free via this link: 

Abstract:

The Accelera Universal Verification Methodology (UVM) became an IEEE standard published as IEEE 1800.2 – IEEE Standard for UVM Language Reference Manual (LRM).  UVM has been the predominant verification methodology for ASIC designs for many years and has recently gained popularity and usage with FPGA designs. 

UVM can improve interoperability and reduce the cost of reusing and integrating IPs. Think of lego-like verification process based on pre-built pieces/components/IPs - that’s precisely what UVM provides to design teams. Learning UVM can take a long time especially if one were to go by the extensive information provided in the LRM. In this webinar, we will cover the basics of UVM and how to get more productive with tips, tricks and techniques. We will walk through basic UVM features from a typical end-user perspective and learn to build a small testbench with UVM. 

Agenda: 

• What is UVM?
• Why UVM?
• UVM top-down and bottom-up view
• UVM macros – brief introduction
• UVM transaction models
• UVM  Driver
• UVM Monitor
• UVM Sequencer 
• UVM Agent
• UVM Env
• UVM Test
• UVM Sequences
• Details of Aldec solution
• Live demo
• Conclusion
• Q&A